1. Field of the Invention
This invention relates to a matrix type liquid crystal display device, and more particularly to a method of driving a liquid crystal panel including thin film transistors and an apparatus thereof.
2. Description of the Prior Art
Generally, in a matrix type liquid crystal display device with thin film transistors, the thin film transistors are provided in the liquid crystal display panel. This matrix type liquid crystal display device can produce a high contrast display even when driven at a low duty ratio or duty cycle in a multiple-line multiplex driving mode. As shown in FIG. 1, the matrix type liquid crystal display device consists of a liquid crystal panel 10 having a plurality of thin film transistors and a plurality of liquid crystal cells, and a scanning side driving circuit 12 and a signal side driving circuit 14 which are connected to the liquid crystal panel 10. The scanning side driving circuit 12 supplies a scanning voltage to a scanning wiring 11 in the liquid crystal panel 10. This scanning wiring 11 consists of scanning electrodes to which the gate electrodes of the thin film transistors are connected. Further, the scanning wiring 11 intersects with signal wiring 13 consisting of signal electrodes. Each of these signal electrodes is connected to the drain electrodes of the thin film transistors. Meanwhile, the signal side driving circuit 14 transforms display data input through a display data input line 15 into a signal voltage to be supplied to the liquid crystal cells and then supplies the signal voltage to the signal wiring 13. The turn-on and turn-off operations of the thin film transistor are controlled by the scanning voltage. When the thin film transistor is turned on, each the liquid crystal cell charges a signal voltage input via the drain and source electrodes of the thin film transistor from the signal wiring 13. Further, each the liquid crystal cell maintains the charged voltage during a period when the thin film transistor is turned off.
FIG. 2 shows the scanning wiring 11 in the liquid crystal panel corresponding to one line. The gate electrode of the thin film transistor 16 for each of the liquid crystal cells is connected to the scanning wiring 11, and the drain electrode of the thin film transistor 16 is connected to the signal wiring 13 which intersects with the scanning wiring 11. If the scanning wiring 11 corresponding to one line is represented by an electric equivalent circuit, it can be expressed by resistors 18 and capacitors 20 as shown in FIG. 3. Resistors 18 constitute the resistance of the scanning wiring 11 and their value is determined by the material constituting the wiring and the shape of the wiring, such as the width, the length, the thickness, etc. Capacitors 20 has a value obtained by adding the capacitance of the gate electrode of the thin film transistors, the capacitance between electrodes included in the liquid crystal cells, the capacitance between the signal wiring 13 and the scanning wiring 11, and the stray capacitance around the scanning wiring 11, etc. If a scanning voltage, which is a rectangular wave, whose rising time tr and falling time tf are short, is applied to the scanning voltage input terminal, the resistors 18 and the capacitors 20 elongate the rising time tr and the falling time tf of the scanning voltage arriving at the gate electrode of the thin film transistor 16, which is physically distant from the scanning voltage input terminal (i.e., which is positioned at the right end of FIG. 3). In order words, the scanning voltage is delayed proportionally to the propagation distance between the scanning voltage input terminal and the specific stage of the scanning wiring 11. This results in distortion of the voltage at the right stage of the scanning wiring 11 that is far away from the scanning voltage input terminal.
FIG. 4 illustrates distortion when a waveform of the scanning voltage GS is propagated through the scanning wiring. The scanning voltage GS is applied to the scanning voltage input terminal during a period when the signal voltage DS is supplied. At this time, a delayed scanning voltage DGS slowly increasing from the rising edge of the scanning voltage GS appears in the right hand stage of the scanning wiring 11. The thin film transistor positioned in the right hand stage of the scanning wiring 11, which is driven by the delayed gate voltage DGS, turns on when the delayed gate voltage DGS becomes higher than its threshold voltage Vth. In other words, the delayed gate voltage DGS is equivalent to the effective gate voltage EGS delayed by τ1, which corresponds to the product of the resistance of the resistors 18 and the capacitance of the capacitors 20 shown in FIG. 3. The delayed scanning voltage DGS decreases slowly from the falling edge of the scanning voltage GS. The thin film transistor 16 positioned in the right hand stage of the scanning wiring 11 is turned off when the delayed gate voltage DGS becomes lower than its threshold voltage Vth. As a result, an effective gate voltage EGS delayed by a time corresponding to the time constant τ1 is applied to the gate electrode of the thin film transistor 16. With the effective scanning voltage EGS, the liquid crystal cell positioned at the right hand stage of the scanning wiring 11 charges the signal voltage DS, during the period extending from the time point after the rising edge of the signal voltage DS by the time constant τ1 of the scanning wiring 11 until the time from the falling edge of the signal voltage DS by a time corresponding to the time constant τ1 of the scanning wiring 11. In other words, the liquid crystal cell charges a signal voltage of the next line during an interval of the time constant from the falling edge of the scanning voltage GS. Accordingly, the effective charge voltage ECDS charged into the liquid crystal cell may fail to maintain the signal voltage DS and changes by a different voltage ΔVPIXEL between it and a signal voltage to be applied to the next line liquid crystal cell.
FIG. 5 and FIG. 6 are graphs illustrating a voltage change appearing at gate electrodes of thin film transistors 16 when the scanning voltage GS is applied to the scanning wiring 11 of the liquid crystal panel 10. FIG. 5 represents a voltage change on each of the gate electrodes of the thin film transistors 16 during the rising edge of the scanning voltage GS. FIG. 6 represents a voltage change on each of the gate electrodes of the thin film transistors 16 during the falling edge of the scanning voltage GS. As shown in FIGS. 5 and 6, voltages on the gate electrodes of the thin film transistors 16 connected to the scanning wiring 11 are slowly changed. It can be seen from this that a propagation delay amount of the scanning voltage GS in the scanning wiring 11 is large. Due to this propagation delay, a signal voltage DS charged into the liquid crystal cells is distorted. This result in an image displayed on the liquid crystal panel 10 being distorted as well as a light transmissivity in the right side and the left side of the liquid crystal panel 10 being made different. The extent of these disadvantages increases as the length of the scanning wiring 11 is made larger.
One technique for overcoming the above-discussed disadvantages is disclosed in the U.S. Pat. No. 4,649,383, by Makoto Takeda, et al. on Mar. 10, 1987. This pre-scanning method advances time points of the turning-on and turning-off of the thin film transistors connected to the scanning wiring by supplying a pre-scanning voltage PGS one time before the signal voltage DS applied to the signal wiring, as shown in FIG. 7. Accordingly, the voltage charged into the liquid crystal cell is not influenced by the signal voltage DS supplied for liquid crystal cell on the next line. As a result, the free-scanning method could prevent a distortion of an image displayed on the liquid crystal panel, and also causes uniform light transmissivity in the liquid crystal panel.
In the pre-scanning method, however, because the rising edge and the falling edge of the scanning voltage PGS supplied to the scanning voltage input terminal is advanced compared with those of the signal voltage DS, a charging time SWGS of the signal voltage of the liquid crystal cell positioned in the scanning wiring close to the scanning voltage input terminal is reduced, as shown in FIG. 7. Also, a charge characteristic of the liquid crystal cells close to the scanning voltage input terminal becomes different from that of the liquid crystal cells far away from the scanning voltage input terminal. This results in the distortion image displayed on the liquid crystal panel being as well as a non-uniform light transmissivity in the liquid crystal panel.